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Commercial and Industrial DDR2 512Mb SDRAM

NT5TU32M16FG-AC的功能

NT5TU64M8FE/NT5TU32M16FG

 Functional Descriptions

 The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536, 870,912

 bits.

 Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a selected location and

 continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration

 of an Activate command, which is followed by a Read or Write command. The address bits registered

 coincident with the activate command are used to select the bank and row to be accesses(BA0-BA1 select

 the bank, A0-A13 select the row). The address bits registered coincident with the Read or Write command are

 used to select the starting column location for the burst access and to determine if the Auto-Precharge

 command is to be issued.

 Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed

 information covering device initialization, register definition, command description and device operation.

NT5TU32M16FG-AC的特性

Features

●Basis DDR22 Compliant

●Data Integrity

- Double-data- rate on DQs,dqs, DM bus

 Auto Refresh and Self Refresh Modes

 4n Prefetch Architecture

●Power Saving Modes

 .Throughput of valid Commands

 Power Down Mode

 -Posted CAS and Additive Latency(AL)

 Partial Array Self Refresh(PASR)

●Signal Integrity

 .SSTL_18 compliance and Power Supply

 -Configurable DS for system compatibility

- VDDDDQ=1.70to1.90v

- Configurable On-Die- Termination

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